1. Field of the Invention
The present invention relates to a layout verification method of verifying layouts of semiconductor integrated circuits and a program thereof, as well as a layout verification apparatus.
2. Description of the Background Art
Recently, to comply with high integration and miniaturization of semiconductor integrated circuits, a rapid progress has been made in miniaturizing resist patterns formed on wafers and mask patterns for forming the resist patterns. In photolithography technique, in order to increase resolution as miniaturization is advanced, super resolution technique is being used as a method other than reducing the wavelength of a light source. As the super resolution technique, there are techniques called xe2x80x9cLevenson methodxe2x80x9d and xe2x80x9cmodified illumination method,xe2x80x9d respectively.
These methods comply with the miniaturization as follows. In Levenson method, a phase shifter is disposed on a mask to increase the resolution of a resist pattern to be formed on a wafer. In the modified illumination method, the shape of a light source itself is changed to increase the resolution of a resist pattern to be formed on a wafer. The use of these super resolution techniques permit a further miniaturized resist pattern, however, there might occur a dimensional variation different from that in conventional ones.
Specifically, in the method using no super resolution technique, it is arranged to prohibit layouts below resolution limitations of the line width of a wiring pattern and the space width (spacing width between lines). This provides a mask pattern layout on which the line width and the space width are both above the resolution limitations. As a result, there occurs no large dimensional variation between the mask pattern and a pattern to be formed on a resist (i.e., the finished pattern), and the dimensional variation of the finished pattern falls within a predictable range.
On the other hand, when using the super resolution technique, the resolution limitations of the line width and space width can be made small. However, in a certain dimensional range, the finished pattern dimension is far larger or smaller than a mask pattern. In some cases, the finished pattern dimension exceeds a permissible limit. It is also difficult to predict this.
Referring to FIG. 16, as is usual in manufacturing semiconductor devices, a circuit design and operation verification of the designed circuit are performed (step S101), followed by a layout design of a mask pattern for forming the circuit on a wafer (step S102). Subsequently, it is verified whether the layout thus obtained is proper or not (step S103), followed by a wafer making process (step S104).
In performing the layout design, it is required not be in contravention of (i.e., be free from errors in) a design rule (referred to as xe2x80x9cDRxe2x80x9d in some cases) R1 that is determined based on restrictions of a process to be used. Hereat, the design rule is used in the layout design and layout verification in steps S102, S103, to specify the line width of wiring and the space width between wirings. Also, the design rule is to be limited by the wafer process.
In performing the layout verification, a design rule check (DRC) C1 is performed to check, for example, whether the designed layout is in accordance with the design rule R1.
Thus, the technique comprising making a predetermined rule and verifying a layout based on the result of checking whether it is contravention of the rule, is called xe2x80x9crule base verification.xe2x80x9d In the present circumstances where the above-mentioned super resolution technique is generally used, the design rule R1 to be employed in the rule base verification is considerably complicated.
When using no super resolution technique in photolithography that is an exemplary wafer process, a design rule for the same layer is relatively simple. That is, the design rule is obtained only by specifying a minimum line width and a minimum space width, which indicate the limitation of the wafer process (e.g., the resolution limitation in photolithography technique).
On the other hand, when using the super resolution technique in a wafer process, a complicate design rule is required to comply with this technique. For instance, when forming a plurality of wiring patterns paralleling and having plural types of space widths, mere specifying of a minimum line width and a minimum space width is insufficient. It is therefore required to judge whether resolution is possible in a combination of a line width and a space width, that is, whether the finished pattern dimension exceeds a permissible limit.
Further, situations arise where no rule can be made, and the incidence of errors might be overlooked. Since the rule specifies the degree to which a pattern deviates, versatility is poor, thus making it difficult to comply with every pattern.
To overcome this problem, recently employed is a technique using optical simulation, which is called xe2x80x9cmodel base verification.xe2x80x9d
The optical simulation is technique of predicting the shape of a finished pattern of layout. Therefore, in the model base verification, a design rule complying with the super resolution technique can be made based on the predicted finished pattern shape. The actual simulation enables to understand exactly every layout pattern and its surrounding situations. Although the degree to which the pattern formation deviates depends on the simulation accuracy, this is recognizable with considerably more accuracy than the rule base verification.
However, the model base verification suffers from the drawback that, due to optical simulation, quite a long time is needed in predicting a finished pattern shape, thereby making it difficult to perform sufficient process evaluation such as the degrees of a defocus margin and an exposure margin.
Upon this, a technique of combining the model base verification and the rule base verification has been proposed. In this technique, optical simulation of the finished pattern of each layout is not performed design by design. In advance, the components of a pattern are subjected to optical simulation under a certain standardized conditions. Then, the design rule obtained by the simulation is applied to verification, thereby increasing verification accuracy and also reducing the time required therefor. Process evaluation can be performed with ease by associating the amounts of a defocus margin, an exposure margin or the like with the rule of components forming each pattern, although this makes the design rule complicated.
FIGS. 17 and 18 are diagrams illustrating an exemplary method of process evaluation in the verification technique mentioned above. This method is, for example, described in Japanese Patent Application Laid-Open No. 2001-014376 (2001).
Referring now to FIG. 17, each wiring pattern such as of wirings and gate electrodes is expressed by graphic data called xe2x80x9cpolygon.xe2x80x9d FIG. 17 exemplifies four polygons P11, P22, P33 and P44. Each polygon is made up of a plurality of sides that are called xe2x80x9csegment.xe2x80x9d For example, the polygon P11 is made up four sides of the segments Seg1 to Seg4.
In the process evaluation, there has been employed a method of making a matrix table, as shown in FIG. 18. To complete the matrix table, optical simulation is performed segment by segment, to obtain its evaluation data. FIG. 18 shows a data table called xe2x80x9cL (line)/S (space) matrix,xe2x80x9d on which the ordinate and abscissa represent a plurality of numerical values of line widths and space widths of a wiring pattern, respectively, for convenience in understanding a plurality of combinations of line width and space width.
In FIG. 18, the ordinate indicates the numerical values of line widths (unit: xcexcm), on which the numerical values from 0.14 xcexcm to 0.4 xcexcm are graduated in 0.02 xcexcm, the numerical values from 0.4 xcexcm to 1.2 xcexcm are graduated in 0.1 xcexcm, and the last value is not less than 1.5 xcexcm. The abscissa indicates the numerical values of space widths, and they are likewise graduated as the line widths.
In addition to data of the possibility of resolution with respect to the wiring pattern, various data as shown in FIG. 18, which are obtained by experiments or simulations, are stored in each cell of the L/S matrix. As example of the various data, FIG. 18 illustrates an original dimension of an L/S pattern, its finished dimension, a difference between the original dimension and the finished dimension, a defocus margin, an exposure margin, a dimple margin, an OPC (optical proximity correction) amount, and other data.
This L/S matrix is used as follows. First, a certain segment is selected, and a line width and a space width, which are defined as a distance in the normal direction up to other segment, are judged from each layout pattern. In FIG. 17, for instance, the segment Seg1 has a line width of L2 and a space width of S1. The segment Seg2 has a line width of L1 and a space width of S2. The next step is to find from the L/S matrix a cell corresponding to the line width L2 and the space width S1. Then, the selected segment is subjected to, for example, evaluation of margin by referring to the various data stored in the corresponding cell.
Thus, the use of the L/S matrix makes it easy to perform process evaluation. In this respect, the L/S matrix is a matrix data storing the conditions under which resolution can be performed.
However, in some cases, it is not so easy to determine the line widths and space widths of segments, as in FIG. 17. Consider now the following layout with reference to FIG. 17. When the length of polygon P33 is smaller than the length of polygon P11, namely line width L2, (e.g., when the length of the polygon P33 is only about a half of the line width L2), the space width of segment Seg4 may not always be S4.
Even in this case, the space width of the segment Seg4 has conventionally been regarded as S4, because each side of a polygon has been simply taken as a segment. Hence, there is room for improving verification accuracy.
According to a first aspect of the invention, there is provided a layout verification method using a layout data of a semiconductor integrated circuit, the layout data containing plural polygons indicating wiring patterns, the polygons being made up of plural segments that are sides, the method comprising the steps of: (a) dividing plural segments forming one of the plural polygons in the layout data, based on a predetermined rule defined beforehand relative to the layout of other surrounding polygon; (b) with respect to the segments divided and segments not divided, detecting a width of wiring containing each of the segments and a width of space most adjacent to each of the segments; (c) evaluating the possibility of resolution of each of the segments by referring to data of conditions under which resolution can be performed, in which a predetermined conditions relative to the possibility of resolution of the segments in a wafer process is stored in association with a combination of the width of wiring and the width of space; and (d) outputting an error information when there is a segment of which possibility of resolution is negative based on the result of evaluation in the step (c).
According to a second aspect of the invention, the layout verification method of the first aspect is characterized in that the predetermined rule means that no division is performed when one segment is, over its entire length, most adjacent to the other polygon, and division is performed when one segment is, only in part of its length, most adjacent to the other polygon within a predetermined distance.
According to a third aspect of the invention, the layout verification method of the first aspect is characterized in that a layout correction amount of the segments is stored in the data of conditions under which resolution can be performed; and that there is added the step of: (e) when the error information is outputted in the step (d), correcting by the correction amount the layout of a segment of which possibility of resolution is negative, while referring to the data of conditions under which resolution can be performed.
According to a fourth aspect of the invention, the layout verification method of the first aspect is characterized in that in the combination of the width of wiring and the width of space in the data of conditions under which resolution can be performed, there is included a combination of a width of wiring containing an aimed segment of the segments and a width of space most adjacent to the aimed segment, as well as a width of wiring not containing the aimed segment and/or a width of space not being most adjacent to the aimed segment.
According to a fifth aspect of the invention, the layout verification method of the first aspect is characterized in that the polygons contained in the layout data are wiring patterns of oblique lines where the wiring and the space are disposed obliquely at a predetermined angle on a plane.
According to a sixth aspect of the invention, the layout verification method of the first aspect is characterized in that the polygons contained in the layout data are hole patterns taking the width of wiring as a hole diameter and the width of space as a width of space between holes.
According to a seventh aspect of the invention, the layout verification method of the first aspect is characterized in that the predetermined condition is defined based on a defocus margin.
In the first, fifth, sixth or seventh aspect of the invention, in the layout data, each of segments forming one of the plural polygons is divided based on the predetermined rule relative to the layout of its surrounding other polygon. This permits more accurate evaluation in the step (c) for evaluating the possibility of resolution of the respective segments, resulting in a layout verification method that is higher in verification accuracy.
In the second aspect of the invention, the predetermined rule in the step (a) means to perform no division when one segment is, over its entire length, most adjacent to other polygon, and to perform division when one segment is, only in part of its length, most adjacent to other polygon within the predetermined distance. Thereby, in the step (a), a wiring pattern shape can be divided in further detail, while avoiding an increase in the amount of calculation.
In the third aspect, in the step (e), with respect to the segment of which possibility of resolution is negative, its layout is corrected by the amount of correction, while referring to the data of the conditions under which resolution can be performed. This makes it easy to obtain a suitable layout.
In the fourth aspect, in the combination of the wiring width and space width in the data of the conditions under which resolution can be performed, there is included a combination of the width of wiring containing an aimed segment of the segments and the width of space most adjacent to the aimed segment, as well as the width of wiring not containing the aimed segment and/or the width of space not being most adjacent to the aimed segment. This permits evaluation that is based on close consideration of the wiring width and space width in the surroundings of the segments.
It is an object of the present invention to provide a layout verification apparatus and a layout verification method, each employing an L/S matrix to achieve higher accuracy of verification, as well as a program thereof.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.